Efficient Power Delay Product Realization of Montgomery Multiplier Based on Pentanomials

Authors:VELLANKI JAGANNADHA RAO, M. SRIHARI

0001-0004

Design & Implementation of VGA Display System Based on CPLD and Dual Memory

Authors:G. SRAVANTHI, DR. M. GURUNADHA BABU

0005-0009

Design of Area Optimized Spanning Tree Adder using Quaternary Logic

Authors:ERUDI VENKATA PUSHPA LATHA, M.SATEESH BABU

0010-0017

Power Optimized Realization of On Chip Network using OCP Protocol

Authors:SANDHYA KUMARI PYLA, A.JAYA VANI

0018-0024

Implementation of Motion Estimation Testing Applications Based On Error Detection and Data Recovery Architecture

Authors:M. RAKESH GOUD, P.SIREESHA

0025-0030

Designing of Low Power ECRL Based Fine-Grain Power-Gated Logic for Asynchronous Circuit

Authors:P. SUNITHA, K. SANTOSH KUMAR

0031-0037

Realization of Multiplexer Based Digital Comparator for Low Power Applications

Authors:LOLABHATTU H S ESWARI, M. SATEESH BABU

0038-0042

Low Leakage and Ground Bounce Noise Reduction for Sleep Transistor Based CMOS Design in Submicron Technologies

Authors:CH. NAVEEN KUMAR, DR.S.BALAJI

0043-0049

A VLSI Based Design of Reduced Power On-Chip Coarse-Grained Network Processor

Authors:MELLAM USHA RANI, R.SATHYA VENI

0050-0053

Implementation of Hold Enabled BIST Controller for Fault Detection in Circuits Implemented on FPGA

Authors:G.TRINATH, G.PRASAD ACHARYA

0054-0058